Implementation and Analysis of a 15-Level Inverter Topology With Reduced Switch Count

Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing switch count and stress on power electronic switches while maintaining sinusoidal stepped output remains challenge. A multilevel inverter topology has been proposed in this work which utilizes twelve four dc voltage sources produce 15-level staircase waveform. The objective is reduce harmonic thereby reducing cost filter requirement high efficiency throughout operating range. Control done using Nearest Level Pulse Width Modulation Strategy (NLPWM). Simulation hardware implementation under different loads dynamic conditions are presented validate robust performance.